Peking University Microprocessor Development and Research Center Selects Mentor Graphics PCI Express IP
WILSONVILLE, Ore.—(BUSINESS WIRE)—May 27, 2005—
Mentor Graphics Corporation (Nasdaq:MENT), a leader in
standards-based semiconductor intellectual property (IP), today
announced its IP core based on the PCI Express architecture has been
selected by the Microprocessor Development and Research Center (MPRC)
of Peking University. Mentor's PCI Express IP was selected based on
its superior configurability and performance of root, switch and
endpoint applications, and will be used for the next-generation I/O
architecture of MPRC's renowned microprocessor technology.
MPRC serves as China's primary research center for computer
science, technology and microelectronics, and it has established a
joint laboratory with Mentor Graphics for system-on-chip (SoC)
verification, chip prototyping and hardware-software debugging. This
joint laboratory also supports IP applications for chip design, which
is why MPRC selected Mentor Graphics' fully-compliant IP for the PCI
Express standard.
Using compliant IP for the PCI Express standard enables design
engineers to focus on the differentiating aspects of their design and
accelerate design time with highly configurable, reusable, low-cost IP
building blocks to create innovative electronic systems. Mentor
recently announced that its configurable port for the PCI Express
specification met compliance by the PCI-SIG organization (see press
release "Mentor Graphics Configurable Port is Compliant with the PCI
Express Specification," April 13, 2005).
"We selected Mentor Graphics based on its history and expertise in
certified, standards-based IP and its ease of integration for complex
SoC designs," stated Xu Cheng, director of Microprocessor Research and
Development Center of Peking University. "PCI Express is an emerging
standard, and our latest microprocessor design will support
applications for networking connectivity."
"Mentor is honored to have been selected by this prestigious
research center and we look forward to supporting Peking University in
the future," stated Mike Kaskowitz, general manager of Mentor Graphics
IP division and VSIA president. "We believe China is on the forefront
of innovative microprocessor designs, and Mentor is fully committed to
ensuring design and verification success by being a key contributor to
this research and development center."
Mentor Graphics IP Solution for PCI Express
Mentor's synthesizable core implements the PCI Express
specifications in a highly configurable block that provides
transaction layer, data link layer, and media access controller (MAC)
functionality down to the physical layer interface (PHY) for the PCI
Express interface (PIPE). For added flexibility, the core can
implement L1 and L2 features of the ASI specification and there is an
option of operation either as a root or as an endpoint with the choice
made at boot time.
The Mentor Graphics IP core for PCI Express implements a rich set
of features in hardware, including end-to-end cyclic redundancy check,
advanced error reporting , hot plugging, power management, crosslink,
lane reversal, message signal interrupt, and cut-through. Engineers
are able to vary the number of lanes, virtual channels, and traffic
classes. The core offers configurable buffer resources for each
channel and data link layer retry.
Additional features include:
-- Scalable architecture: x1, x2, x4, x8 lanes at 2.5 Gbps
-- Up to 4,096 byte packets for Tx and Rx and retry buffers
-- 64- FIFO-based back-end interface
-- 8- or 16-bit PIPE interface to SerDes PHY
-- Configurable Port for PCI Express specification is available
in Verilog source code with a high-level functional testbench
and documentation
-- Complementary to Mentor Graphics verification products such as
the iSolve(TM) speed adapter and the ModelSim(R) verification
environment for PCI Express specification
-- Interoperable with the Rambus Raser PHY
Mentor Graphics Silicon-Proven, Standards-Based Intellectual
Property
Mentor Graphics offers a variety of industry-leading,
standards-based IP cores that are rigorously tested and validated to
provide design teams with the most reliable cores in the industry.
Mentor's IP portfolio ranges from simple SoC building blocks, such as
communications interfaces and microcontrollers, to an expansive
offering of products for ethernet, USB, storage and PCI Express. To
find out more about Mentor's intellectual product offerings, visit
www.mentor.com/products/ip/.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in
electronic hardware and software design solutions, providing products,
consulting services and award-winning support for the world's most
successful electronics and semiconductor companies. Established in
1981, the company reported revenues over the last 12 months of over
$700 million and employs approximately 3,850 people worldwide.
Corporate headquarters are located at 8005 S.W. Boeckman Road,
Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are
located at 1001 Ridder Park Drive, San Jose, California 95131-2314.
World Wide Web site: http://www.mentor.com/.
ModelSim is a registered trademark and iSolve is a trademark of
Mentor Graphics Corporation. All other company or product names are
the registered trademarks or trademarks of their respective owners.
Contact:
Mentor Graphics Corporation, Wilsonville
Larry Toda, 503-685-1664
larry_toda@mentor.com
Suzanne Graham, 503-685-7789
suzanne_graham@mentor.com
